1. Field of the Invention
The present invention relates to a refresh controlling method and a refresh controlling apparatus, and more particularly, to a refresh controlling method, by which a refresh interval may flexibly vary depending on a current state of an internal bus in a controller chip by performing a refresh operation when a bus blank period is detected, before a regular refresh interval has completely lapsed.
2. Description of the Related Art
General dynamic RAMs (DRAMs) includes a plurality of cells, each of which is composed of a capacitor and a transistor. The transistor charges the condenser with electricity or discharges the electricity from the condenser. DRAMs store data in the condenser. Since the compacitor loses data due to a spontaneous electricity discharge after a lapse of a predetermined period of time, for example, about 2 ms, a refresh control circuit is required to prevent the data loss.
FIG. 1 is a block diagram of a structure of a conventional refresh controlling apparatus 100 and a peripheral unit thereof, namely, a bus mediator 120. The conventional refresh controlling apparatus 100 includes a storage unit 111, a counter 113, a comparator 115, and a refresh signal generator 117. The bus mediator 120 mediates the right of use of an internal bus in a chip among a plurality of bus master devices.
In the refresh controlling apparatus 100, the storage unit 111 receives a refresh interval 131 and stores the same in synchronization with a system clock 132. The refresh interval 131 is obtained by dividing a refresh period of a currently used DRAM by a number of rows. The counter 113 performs down or up counting on a refresh interval 133, which is stored in the storage unit 111, in synchronization with the system clock 132. The comparator 115 compares a count value 135, which is output from the counter 113, with a refresh interval 134, which is output from the storage unit 111. If the count value 135 is equal to the refresh interval 134, the comparator 115 generates a bus request signal 136 and outputs the same to the bus mediator 120. The bus mediator 120 generates a bus approval signal 137 in response to the bus request signal 136. In response to the bus approval signal 137, the refresh signal generator 117 generates a refresh command or a refresh informing signal. According to this structure, the refresh controlling apparatus 100 refreshes each row of a DRAM at a refresh interval, which is obtained by dividing a refresh period for each DRAM by a number of rows of memory cells.
As described above, a DRAM must periodically perform a refresh operation in order to prevent loss of the data stored in each cell. Hence, when a controller chip is designed using the DRAM as a data storage device, a refresh controlling apparatus is included and used as a bus master device. A typical controller chip includes at least two bus master devices, such as a CPU, a DMA controller, etc. The bus mediator 120 mediates the right of use of a bus according to the priority of the bus master devices. However, if each of the memory cells of a current memory is not properly refreshed during a predetermined refresh period, data stored in the current memory may be lost. Accordingly, there is a tendency to give the refresh controlling apparatus 100 a priority over the other bus master devices.
In this case, if a refresh controlling apparatus and other bus master devices simultaneously request the use of an internal bus of a controller chip, the refresh controlling apparatus preferentially has a bus usage right, while the other bus master devices cannot use the internal bus until the refresh controlling apparatus completes its refresh operation. Thus, as a number of collisions between bus usage requests of the refresh controlling apparatus and the other bus master devices increase, efficiency of the use of the internal bus of the controller chip degrades. Degradation of a performance of the internal bus leads to a deterioration of a performance of the controller chip.